Our Editors-in-Chief’s Top Picks
The Editors-in-Chief of our CASS publications have selected some noteworthy papers from the recent issues of our journals:
IEEE Transactions on Circuits and Systems I: Regular Papers
Paper 1:
R. Xia et al., "An 8-ppm/°C 100-MHz RC Oscillator With Implicit Temperature Compensation and Resistor Aging Characterization," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 6, pp. 3962-3974, June 2026. https://ieeexplore.ieee.org/document/11359996
Summary: The rapid growth of the Internet of Things (IoT) has fueled demand for compact, low-cost, and energy-efficient integrated circuits used in microcontrollers, wireless sensors, and wearable devices. At the heart of these systems are on-chip RC oscillators, which provide essential timing without requiring bulky external crystal resonators. However, their frequency accuracy can drift with temperature changes and long-term device aging, limiting reliability in real-world environments. This work presents a new approach that stabilizes oscillator frequency by exploiting a naturally temperature-insensitive operating point, supported by detailed analysis and comprehensive long-term aging characterization to enable robust RC oscillator design.
Paper 2:
R. Gómez-García et al., "Reflectionless Design in RF Passive and Active Circuits: Recent Advances and Emerging Trends," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 7, pp. 4482-4495, July 2026. https://ieeexplore.ieee.org/document/11419670
Summary: Modern wireless systems—from 5G/6G communications and radar to quantum technologies—depend on RF circuits that can process signals with maximum efficiency and reliability. A major challenge is unwanted signal reflections, which can distort information and limit overall system performance. This paper reviews the rapidly-growing field of reflectionless RF design, where circuits absorb unwanted signals instead of reflecting them back. Beyond summarizing recent advances in filters, integrated circuits, and amplifiers, it highlights emerging applications in antennas, electromagnetic compatibility, and quantum engineering. Reflectionless technology is opening new pathways toward smarter, more robust, and highly integrated future communication, sensing, and quantum systems.
IEEE Transactions on Circuits and Systems II: Express Briefs
Paper 1:
Yizhou Zhao , Xinyu Zhao, Yuan Shen, Chengxiang Zheng, En Zhu, and Yingmei Chen, “A 56-Gb/s 10.46-pA/sqrt_Hz Input Noise Linear TIA With 31-dB Dynamic Range in 22-nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 73, no. 4, pp. 448 - 452, Apr. 2026. doi: 10.1109/TCSII.2026.3669591
Summary: The rapid growth of AI and cloud services demands optical interconnects capable of transmitting data beyond 56 Gb/s. At the core of these links is a transimpedance amplifier, which converts optical signals into electrical signals. Our design introduces a novel wide dynamic range TIA that allows to dynamically adjust its operating point, maintaining a stable bandwidth even when the input optical power varies by more than 30 dB. Fabricated in a standard 22-nm CMOS process, it achieves an input-referred noise density of just 10.46 pA/√Hz together with high linearity. This work enables optical receivers that are both highly sensitive to weak signals and robust enough to handle strong ones, contributing to more efficient data centers.
Paper 2:
Jingbin Feng , Shanshan Zhou , Peiru Hou, Pengda Qu , Yue Zhao , and Zhiming Xiao, “A 60-V Chopper Amplifier Achieving 0.12-uV Ripple and 2-uV VOS Over Full Temperature With Calibration,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 73, no. 4, pp. 368 - 372, Apr. 2026. doi: 10.1109/TCSII.2026.3663261
Summary: This work presents a 60 V chopper-stabilized operational amplifier (opamp) with an 8 MHz gain-bandwidth product (GBW) and precision calibration. A high-voltage adaptive clock-bootstrap technique is proposed, compensates for temperature variations of the threshold voltage, and maintains a constant overdrive voltage. The opamp integrates a gain module to amplify and calibrate the non-chopped offset voltage, thereby reducing output ripple. It adopts a calibration scheme with temperature-compensated bit weights which are proportional to the transconductance of the chopper-path input transistor pair. Fabricated in a 0.18- m Bipolar-CMOS-DMOS process, the amplifier employs input-referred offset and ripple minimization techniques while ensuring consistent performance over a wide input common-mode voltage range and temperature span, achieving a 3- offset voltage of V across 100 samples (- C to C), an offset drift of 7 nV/°C, and a maximum input-referred ripple of VRMS(Root Mean Square).
Paper 3:
3. Wanqing Wu , Xinyi Zhang , Ning Zhang, Ruiyong Xiang , Haigang Feng , and Zhihua Wang, “A 16-to-24.9 GHz Dual-Core Dual-Mode Noise-Circulating VCO Using Single-Phase Switch With FOMT of 209.0 dBc/Hz,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 73, no. 5, pp. 508 - 512, May. 2026. doi: 10.1109/TCSII.2026.3669392
Summary: This work presents a dual-core dual-mode noise-circulating voltage-controlled oscillator (VCO) with a wide frequency tuning range (FTR) and low phase noise (PN) for K-band applications. Specifically, the VCO employs an optimized capacitively coupled noise-circulating structure to operate in the K-band while suppressing the thermal noise contribution of the transistors. Fabricated in a 65-nm CMOS process, the VCO occupies an active core area of 0.096 mm2. When operating at 16.32 GHz, the VCO achieves -148.4 dBc/Hz at 10 MHz offset frequency after the frequency is divided by three. While the power consumption is 4.9 mW from a 0.9 V supply, the resulting figure-of-merit (FOM) is 196.2 dBc/Hz. With a FTR from 16 GHz to 24.9 GHz (43.5%), the VCO achieves a FOM with tuning range (FOM ) of 209.0 dBc/Hz.
IEEE Transactions on Circuits and Systems for Video Technologies
Paper 1:
Yimin Fu, Runqing Yang, Zhunga Liu, Michael K. Ng. "Adaptive Mixture-of-Experts Distillation for Cross-Satellite Generalizable Incremental Remote Sensing Scene Classification," IEEE Trans. on Circuits and Systems for Video Technology, vol.36, no.1, pp.233-247, Jan. 2026. doi: 10.1109/TCSVT.2025.359827.
This paper proposes adaptive mixture-of-experts distillation (AMoED) for cross-satellite generalizable incremental remote sensing scene classification (CS-GIRSSC). Specifically, AMoED adopts a high-level semantic learning pipeline, in which new knowledge is acquired through the coordinated guidance of multiple domain-specific experts, rather than directly from raw data. This pipeline prevents the model from being exposed to large volumes of newly emerging data, thereby alleviating the erasure of previous knowledge when adapting to new data distributions. Besides, the adaptive mixture of domain-specific experts facilitates the formation of universal class concepts, which exhibit strong generalizability across different domains. During the learning process, an equi-partite subset is constructed for knowledge acquisition and consolidation, accompanied by a shallow style-mixing operation to mitigate the interference of domain discrepancies. Extensive experiments have been conducted on four remote sensing scene classification datasets, and the method proposed in this paper consistently shows state-of-the-art performance across various scenarios and settings. The code has been also made available by the authors at https://github.com/fuyimin96/AMoED
Paper 2:
Xiao Wang, Chao Wang, Shiao Wang, Xixi Wang, Zhicheng Zhao, Lin Zhu. "MambaEVT: Event Stream-Based Visual Object Tracking Using State Space Model," IEEE Trans. on Circuits and Systems for Video Technology, vol.36, no.1, pp.278-291, Jan. 2026. doi: 10.1109/TCSVT.2025.3588533.
This paper proposes a Mamba-based visual tracking framework that adopts the state space model with linear complexity as a backbone network. The search regions and target template are fed into the vision Mamba network for simultaneous feature extraction and interaction. The output tokens of search regions will be fed into the tracking head for target localization. More importantly, a dynamic template update strategy is introduced into the tracking framework using the Memory Mamba network. By considering the diversity of samples in the target template library and making appropriate adjustments to the template memory module, an effective dynamic template can be integrated. The effective combination of dynamic and static templates allows the proposed Mamba-based tracking algorithm to achieve a good balance between accuracy and computational cost on multiple large-scale datasets, including EventVOT, VisEvent, and FE240hz. The source code and checkpoint of this work have been released on https://github.com/Event-AHU/MambaEVT
Overview of the proposed pure Mamba-based visual object tracking using an event camera, termed MambaEVT. The vision Mamba based backbone network performs feature extraction, interaction and fusion, simultaneously. It ensures the tracker achieves good performance and lowers computational cost. The learnable Memory Mamba for dynamic template generation makes the tracker more robust to significant appearance variation.
Paper 3:
Nian Wang, Zhigao Cui, Yanzhao Su, Yunwei Lan, Yuanliang Xue, Cong Zhang. "Weakly Supervised Image Dehazing via Physics-Based Decomposition," in IEEE Trans. on Circuits and Systems for Video Technology, vol.36, no.1, pp.637-652, Jan. 2026, doi: 10.1109/TCSVT.2025.3596024.
This paper proposes a weakly supervised image dehazing (WSID) model via physics-based decomposition (PBD). The proposed approach estimates atmospheric light, scattering coefficient and scene depth of real haze input to effectively capture the illumination information and haze distribution to recover a preliminary dehazed image by minimizing reconstruction loss. With this constraint, a subtly discrete wavelet discriminator (DWD) is designed to effectively improve the generalization to real scene from both spatial and frequency aspect under the supervision of unpaired real clear image. The PBD is a purely data-driven model freeing from any manual setting or partially correct prior, thus simultaneously ensuring the realness and visibility of dehazed images. Experiments on seven benchmarks have been reported in the paper showing the strong generalization ability of the proposed PBD, which achieves SOTA dehazing performance with realistic details. The code has been made available by the authors at the following link at https://github.com/NianWang-HJJGCDX/PBD
Workflow of the PBD proposed in this paper. First, four generators are used to yield the dehazed image Jout, scattering coefficient β, scene depth D, global atmospheric light A. The β and D capture the haze distribution of input real haze image Ireal and obtain a refined transmission map T. Reconstruction loss is used to constrain the structure information of these parameters. Then DWD improves the generalization ability of Jout and makes it fit in various real haze scenes via the adversarial training from both spatial and frequency aspect.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Paper 1:
V. K. Bose, R. V. Joshi, Y. Cao and B. J. Kailath, "ShiftMUX: Reconfigurable 4:1 MUX-Based In-Memory Shifter for Multiplication-Less Deep Neural Network Accelerations," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 16, no. 2, pp. 327-337, June 2026. https://ieeexplore.ieee.org/document/11318555
Summary: This paper presents ShiftMUX, a reconfigurable 4:1 multiplexer (MUX)-based in-memory computing (IMC) architecture for multiplier-less deep neural network (DNN) acceleration. The proposed design completes its operation in only three cycles, compared with at least ten cycles in prior approaches. Beyond basic logic, ShiftMUX supports complex functions such as full adder, full subtractor, and comparator, eliminating the need for separate mapping and control peripherals. When cascaded in a crossbar, multiple MUX units realize N -bit shift operations including logical, arithmetic, circular, and universal shifts enabling efficient power-of-two multiplications for quantized DNNs. Circuit-level simulations in 45 nm technology show write energy of 32 pJ, read delay of 9.14 ps, and a total energy consumption of 240 pJ for a 4-bit multiplier, outperforming state-of-the-art designs. A Vision Transformer model exhibits only a + 2.66% accuracy deviation with shift-based multiplication, confirming the suitability of ShiftMUX for modern AI models. Moreover, the architecture reduces computation overhead by more than 90%, requiring only N+log2 (N)+2 cycles, and achieves up to 9×speedup in multiplication. ShiftMUX thus provides a scalable, reconfigurable, and energy-efficient solution for low-latency DNN acceleration in edge and high-performance computing systems.
Paper 2:
Y. -X. Zhang, S. Yang, Y. -H. Ren, S. Chen and P. Zhang, "In-Memory Computing-Based Ultra-Efficient Massive MIMO Precoding: Memristor Crossbar Circuits, Conductance Mapping Strategies, and Programming Latency Estimation," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 16, no. 2, pp. 525-537, June 2026. https://ieeexplore.ieee.org/document/11316487
Summary: Massive MIMO is a key technology for 5G and future 6G wireless systems, but linear precoding methods such as zero-forcing and minimum mean square error precoding require matrix inversion, which creates substantial latency and energy overhead in baseband processing. This paper presents an in-memory computing solution based on memristor crossbar circuits for ultra-efficient massive MIMO precoding. The proposed architecture supports both ZF and MMSE precoding in a unified circuit and enables fast one-step computation without complex timing control. To address practical device limitations, the work develops an optimized matrix-to-conductance mapping strategy that jointly considers memristor conductance constraints and precoding-matrix statistics, reducing relative computation error by more than 60% compared with a baseline mapping scheme. It also introduces a probabilistic programming-latency model that captures potentiation and depression dynamics and provides closed-form latency estimates validated by Monte Carlo simulations. System-level results show that the proposed circuit achieves BER close to 64-bit floating-point precoding while providing over 100× improvements in energy and area efficiency compared with baseline commercial GPUs.
Paper 3:
W. -J. Tsai et al., "A Page-Buffer and Fail-Bit Counter-Based In-Memory Computing Platform for 3-D NAND Flash Memory," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 16, no. 2, pp. 617-628, June 2026. https://ieeexplore.ieee.org/document/11369267
Summary: We propose an in-memory computing platform for 3D NAND Flash memory. By re-purposing the existing page buffers and fail-bit counters in the NAND Flash chip, diverse in-memory computing applications such as bulk bitwise operation, in-memory search, and vector similarity search can be realized. The re-design cost is minimized, and its operation is almost comparable to the original NAND Flash’s program, erase, and read operations. It is robust against process, voltage, and temperature variations. By reducing the need for huge and frequent data transfers between storage and the processor, latency and energy efficiency are greatly improved. This design presents an attractive and promising option for in-memory computing applications in NAND Flash memory. Furthermore, it can be applied to other storage or memory devices that possess the page buffers and fail-bit counters suitable for re-purposing..
IEEE Open Journal of Circuits and Systems
Paper 1:
E. Sacchi et al., "8-Channel CMOS Chip for Real-Time Control of Integrated Silicon Photonic Processors," in IEEE Open Journal of Circuits and Systems, vol. 7, pp. 206-217, 2026. https://ieeexplore.ieee.org/document/11304253
Summary: Light moves fast, but programmable photonic processors still need electronics clever enough to keep them on course. In this paper, Sacchi and colleagues introduce an eight-channel CMOS controller that continuously monitors and adjusts silicon photonic interferometers in real time. Using two controller chips, the team independently steered all 15 interferometers in a 16-channel photonic mesh, recovering the optimal optical path from a random starting point in roughly 10–15 milliseconds. This boosted output power by about 23 dB. Even more impressively, the system compensated for simulated atmospheric turbulence and restored free-space optical links carrying 25-Gbit/s and 50-Gbit/s signals. By replacing bulky FPGA-based control hardware with compact, parallel feedback electronics, this work brings scalable, self-correcting photonic processors closer to practical deployment in communications, computing, sensing, and beyond.
Paper 2:
A. Maclellan, L. H. Crockett and R. W. Stewart, "RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training," in IEEE Open Journal of Circuits and Systems, vol. 6, pp. 38-49, 2025. https://ieeexplore.ieee.org/document/10772713
Summary: This work presents a dynamic amplifier that achieves −52 dB in total harmonic distortion through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter incorporating the linearized dynamic amplifier in both the input buffer and the first residue amplifier stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator process.
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IEEE CAS Magazine Third Quarter Issue 2026
IEEE Circuits and Systems (CAS) Magazine publishes original review articles and other articles that are of broad interest to the Circuits and Systems Society community. Interested authors are invited to send a three to four page White Paper first to the Editor-in-Chief, Prof. Keshab K. Parhi, by email here. If invited, they can submit a Full Paper at the Author Portal at the link below. CAS Magazine will continue to publish articles related to CAS Society Outreach. In addition, CAS Magazine also publishes articles related to education (such as tricks in solving problems and short lecture notes), conference highlights, chapter highlights, applications, and standards. Please feel free to submit articles that are of broad interest to the members of the CAS Society. For more information, please visit the IEEE Circuits and Systems Magazine on the CASS website.
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Latest Tables of Contents of CAS Sponsored Journals
The latest issues of our CAS sponored journals have been published and the tables of contents can be accessed through the following links:
- IEEE Transactions on Circuits and Systems I: Regular Papers
- IEEE Transactions on Circuits and Systems II: Express Briefs
- IEEE Transactions on Circuits and Systems for Video Technology
- IEEE Journal on Emerging and Selected Topics in Circuits and Systems
- IEEE Circuits and Systems Magazine
- IEEE Transactions on Biomedical Circuits and Systems
- IEEE Design and Test Magaz